1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method thereof. More specifically, the present invention relates to a complementary metal oxide semiconductor (CMOS) image sensor and manufacturing method thereof.
2. Description of the Related Art
An image sensor, as a kind of semiconductor device, transforms optical images into electrical signals. Image sensors can be generally classified into charge coupled devices (CCD) and CMOS image sensors.
Conventionally, a CCD comprises a plurality of photo diodes arranged in the form of matrix to transform optical signals into electrical signals, a plurality of vertical charge coupled devices (VCCDs) formed between the photo diodes to transmit charges generating in each photo diode in a vertical direction, a plurality of horizontal charge coupled devices (HCCDs) for transmitting charges transmitted from each VCCDs in a horizontal direction, and a sense amplifier for sensing charges transmitted in the horizontal direction to output electrical signals.
It has been generally known that CCDs have relatively complicated operational mechanisms, and high power consumption. In addition, its manufacturing method is relatively complicated, because multiple photolithography processes are required in its fabrication. Especially, it is difficult to integrate a CCD with other devices such as control circuits, signal processing circuits, analog/digital converters, etc., in a single chip. Such disadvantages of CCDs may hinder miniaturization of products containing a CCD.
In order to overcome above described disadvantages of CCDs, CMOS image sensors have been recently developed in the oncoming generation(s) of image sensors.
Meanwhile, CMOS image sensors can be classified into 3T, 4T, 5T types, etc., according to the number of transistors in a unit pixel. The 3T type CMOS image sensor comprises one photo diode and three transistors in the unit pixel, and the 4T type comprises one photo diode and four transistors in the unit pixel. Here, a unit pixel layout of the 3T type CMOS image sensor is configured as follows.
FIG. 1 shows a layout illustrating unit pixel in a conventional 3T type CMOS image sensor.
As shown in FIG. 1, one photo diode 20 is formed in a large portion of a defined active region 10, and three transistors 120, 130, and 140 are respectively formed to overlap other portions of the active region 10. The transistor 120 constitutes a reset transistor, and the transistor 130 constitutes a driver transistor, and the transistor 140 constitutes a select transistor. Here, dopant ions are implanted in the active region 10 where each transistor is formed, except the portion of active region 10 below each gate electrode of the transistors 120, 130, and 140, to form source and drain regions of each transistor.
A supply voltage (VDD) is applied to source/drain regions between the reset transistor and the driver transistor, and the source/drain regions formed at one side of the select transistor is connected to detecting circuits (not shown). Transistors 120, 130, and 140 are respectively connected to signal lines, even though they are not illustrated in FIG. 1. In addition, signal lines are respectively connected to external driving circuits via additional pads respectively formed at one end thereof.
FIG. 2 shows a cross-sectional view illustrating a photo diode and a reset transistor of a conventional CMOS image sensor, in view of A-A′ line in FIG. 1.
Referring to FIG. 2, P− type epitaxial layer 101 is formed on a P++ type semiconductor substrate 100. In addition, the semiconductor substrate 100 including the epitaxial layer 101 is defined by the active region 10 including the photo diode region PD, as shown in FIG. 1, and an isolation region where isolation layer 102 is formed.
As shown in FIG. 2, the gate electrode 104 for the reset transistor 120 is formed on the epitaxial layer 101 and on a gate insulating layer 103. Nitride sidewalls 110a are formed on sides of the gate electrode 104.
In addition, an N− type diffusion region 106 is formed in the photo diode region PD of the epitaxial layer 101. An N− diffusion region 108 for a lightly doped drain (LDD) structure and an N+ diffusion region 112 for source/drain diffusion regions are formed in the transistor region of the epitaxial layer 101.
A TEOS (Tetra-Ethyl-Ortho-Silicate) oxide 109 is formed over an entire surface of the semiconductor substrate 100 covering the gate electrode 104, and a metal silicide layer 115 is formed on a surface of the source/drain diffusion region 112. Furthermore, a nitride layer 116, functioning as a diffusion and etching blocker, and an interlevel dielectric layer 117 are formed in successive order over the entire surface of the semiconductor substrate 100.
FIGS. 3a to 3i are cross-sectional views illustrating a conventional method for manufacturing a CMOS image sensor.
Referring to FIG. 3a, a P− type epitaxial layer 101 is formed on the semiconductor substrate 100 such as single crystalline silicon having a heavy concentration and a first conductivity type (i.e., P++ type). Here, the epitaxial layer 101 functions to form a deep and wide depletion region in the photo diode region. Thereby, the ability of a low-voltage photo diode for gathering photoelectrons can be improved, and also the light sensitivity can be improved.
In addition, the semiconductor substrate 100 is defined by an active region and an isolation region, and an isolation layer 102 is formed by a shallow trench isolation (STI) process or a local oxidation of silicon (LOCOS) process.
Next, a gate insulating layer 103 and a conductive layer are deposited on the entire surface of the epitaxial layer 101 including the isolation layer 102, in successive order, and they are selectively patterned using photolithography and etching processes, thus forming the gate electrode 104.
A first photoresist layer is then applied over the entire surface of the substrate 100 including the gate electrode 104, and then it is patterned using exposure and development processes, thus forming a first photoresist pattern 105 exposing the photo diode region. Then, using the first photoresist pattern 105 as a mask, a N− diffusion region 106 is formed in the exposed photo diode region by ion-implantation of a low concentration of N type dopant ions.
As shown in FIG. 3b, after removing the first photoresist pattern 105, a second photoresist layer is applied over the entire surface of the substrate 100, and then it is patterned using exposure and development processes, thus forming a second photoresist pattern 107 exposing the transistor region. Then, using the second photoresist pattern 107 as a mask, a low concentration of N type dopant ions are implanted in the exposed transistor region to form a N− type diffusion region 108. Here, the N− type diffusion region 106 of the photo diode region is preferably formed at a diffusion depth greater than that of the N− type diffusion region 108 of the transistor region, using a higher implantation energy.
As shown in FIG. 3c, after removing the second photoresist pattern 107, a TEOS oxide layer 109 is formed over the entire surface of the substrate 100 in a thickness of about 200 Å, and then a nitride layer 110 is formed on the TEOS oxide layer 109. Continuously, an etch back process is performed on the nitride layer 110 to form the nitride sidewalls 110a on sides of the gate electrode 104, as shown in FIG. 3d. 
As shown in FIG. 3e, a third photoresist layer is formed over the entire surface of the substrate 100, and then it is patterned by exposure and development processes, thus forming a third photoresist pattern 111 covering the photo diode region and the isolation layer 102. Continuously, using the third photoresist pattern 111 as a mask, a high concentration of N type dopant ions are implanted in source/drain regions to form the N+ type diffusion region 112.
As shown in FIG. 3f, after removing the third photoresist pattern 111, a heat-treatment process (e.g., a rapid thermal process under a temperature of over 800° C.) is performed to activate dopant ions in the N− type diffusion region 106, the N− type diffusion region 108, and the N+ type diffusion region 112. Next, a silicide blocking layer 113 is formed over the entire surface of the semiconductor substrate 100.
As shown in FIG. 3g, a fourth photoresist layer is applied on the silicide blocking layer 113, and it is patterned by exposure and development processes, thus forming a fourth photoresist pattern 114 exposing the region where a silicide will be formed. Using the fourth photoresist pattern 114 as a mask, the exposed silicide blocking layer 113 and the TEOS oxide layer 109 are selectively removed to expose a portion of the substrate where the N+ diffusion region 112 is formed.
As shown in FIG. 3h, after removing the fourth photoresist pattern 114, a metal layer having a high melting point is deposited and thermally treated to form a metal silicide layer 115 on the exposed surface of the substrate in the transistor region. Subsequently, a remaining metal material, not reacted with silicon, is removed, and the silicide blocking layer 113 is removed.
As shown in FIG. 3i, a nitride layer 116, functioning as a diffusion and etching blocker in the subsequent process(es), is deposited over the entire surface of the substrate 100, and an interlevel dielectric layer 117 is formed on the nitride layer 116. Afterward, power lines, color filter arrays, and microlenses are formed over the interlevel dielectric layer 117 to complete a CMOS image sensor, even though it is not shown in the drawings.
The conventional manufacturing method of a CMOS image sensor generally employs 0.35˜0.18 micron technologies. Furthermore, sub-0.18 microns technologies have been intensively developed for a higher integration of semiconductor devices. In general, super-0.25 microns technologies have a thermal budget, which is caused by a silicidation process. More specifically, because a thermal treatment of over about 800° C. is rarely allowed after forming a silicide layer, it is difficult to remove impurities, which can cause dark currents.
Meanwhile, in the above-described conventional method, a heat treatment for a lightly doped drain structure and a photo diode and a heat treatment for source/drain diffusion regions can be also performed at a high temperature of over 800° C., thus enabling recovery or repair of the lattice-damaged substrate and activating implanted dopant ions. However, the interlevel dielectric layer 117 is required to be thermally treated at a temperature below 700° C. in order to prevent deformation of the metal silicide layer 115 and to form a shallow junction. The interlevel dielectric layer 117 is typically formed using a BPSG (Boron-Phosphorus-Silicate-Glass) material and has a gathering effect on impurities. The gathering effect of the interlevel dielectric layer 117 becomes powerful at a relatively high temperature. However, there is a limit to raise a heating temperature of the interlevel dielectric layer of a BPSG material, for the above-explained reason.
In addition, a diffusion blocker 116 (typically a nitride layer) is formed before forming the interlevel dielectric layer 117. However, as the size/area of the photo diode region decreases according to scale-down of a CMOS image sensor, the nitride layer 116 may cause reduction of dynamic range and light sensitivity of the CMOS image sensor. Thus, the performance qualities of the CMOS image sensor; such as reproducibility, etc., may deteriorate.